1. Field of the Invention
The invention relates to improvements in cache organization in a data processing system which permits a main storage line fetch, cache bypass, line castout and processor cache access to all occur concurrently.
2. Description of the Prior Art
U.S. Pat. Nos. 3,670,307 and 3,670,309, both assigned to the same assignee as the present application, teach an interleaved cache with plural BSM's permitting concurrent access of a processor and a main storage to the cache when their accesses are to different BSM's. Accesses to the same BSM cannot occur simultaneously.
U.S. Pat. No. 4,169,284, assigned to the present assignee, enables a processor to access its cache during any cycle of a line fetch by having the cache cycled at twice the rate that doublewords (DWs) are transferred from either the processor or main storage to cache.
Japanese Published Examined Patent Application No. 53-24260, issued Apr. 12, 1975 provides a data buffer (which is often called a line fetch buffer) serially connected between a main storage and a processor cache. The processor may access a different line or block in the cache while the line is being transferred from the main storage to the line fetch buffer but the line being fetched cannot be accessed by the processor until after the line fetch to the buffer is completed. Then, the processor accesses only the line fetch buffer for data in the fetched line. When the next cache miss occurs, a processor wait results until the requested data is received from the main storage. During the processor wait period, the line in the line fetch buffer is transferred to the cache. The processor cannot access the cache during the line fetch buffer-to-cache transfer of the entire line. The fetched line cannot begin to be put into the cache from the line fetch buffer until the castout line is completely stored in the line fetch buffer. The cache addressable unit and the main storage bus have the same path width. Processor-cache access overlap is obtainable with a line fetch.
None of the prior art teaches the concurrent line castout and line fetch transfers with the main storage.